The present invention relates to a semiconductor device and, more particularly, to a bipolar power transistor.
It is well known in the art that the maximum power that can be dissipated from a bipolar transistor for a given collector-emitter voltage, without causing its failure defines the safe operating area or S.O.A.
It is also well known that, under operating conditions of a bipolar transistor with relatively high voltage values, a phenomenon arises which is known as forward biased secondary breakdown or I.sub.s/b which consists in a focusing of the collector current. If such a phenomenon is triggered, the temperature of the junctions increases without limit, causing a temperature derating and eventual transistor failure. Therefore, one is forced to limit the maximum power that can be dissipated by the transistor. In other words, the safe operating area of the transistor is reduced in order to avoid the phenomenon described above.
Various measures can be adopted in an attempt to limit the negative effects attributable to the I.sub.s/b and thereby to broaden the S.O.A. Particularly known among these measures is the use of ballast resistors in series with the base or with the emitter, or with both; these resistors, since they tend to uniformly distribute the current over the entire base-emitter junction, initiate a reaction which is adverse to the I.sub.s/b phenomenon and, therefore, stabilize the device, enabling it to operate safely at higher power levels.
However, the ballast resistances both in the emitter circuit and in the base circuit cannot be increased above a certain limit, especially in order not to deleteriously affect the saturation voltage of the transistor. Therefore, when designing a power transistor, it is necessary to arrive at the best compromise possible between these two opposing requirements, dependent upon the applications of the device.
From the constructional point of view, in order to design ballast resistors in the base circuit that are inherent in the structure of the transistor, it is necessary to utilize elevated layer resistances. A common method to obtain them consists in the pinching of the base, as exemplified by both British Patent No. 1,482,803 and U.S. Pat. No. 3,860,460. In this case, the diffusion of a region with an N-type conductivity in the base region. having a P-type conductivity located around the emitter area creates an insulated PN junction between the emitter junction and the base contact of the transistor, which offers the advantage of substantially increasing the distributed resistance of the base, but which has the disadvantage, due to the high voltage drop across said resistor, of considerably increasing the base-emitter voltage V.sub.BE of the transistor for high base currents.
As mentioned above, a transistor with a high V.sub.BE is undesirable in many applications, for example, when the transistor is the final transistor of a pair of Darlington-connected transistors. In this case, the collector-emitter saturation voltage V.sub.CEsat which results from the sum of the collector-emitter saturation voltage of the input transistor and of the base-emitter voltage of the final transistor, is very high if the V.sub.BE of the final transistor is high.